For FinFET devices, the source drain regions are merged by growing epitaxy. However, the epitaxy growth process can be non-uniform, defective, and depend on loading effects. In addition, fin sidewall residues, fin shape, fin erosion, pitch walking, and other variations can undesirably impact epitaxy growth. For example, thickness and doping can vary as a function of fin number, which can have a serious impact for static random-access memory (SRAM) cells since the number of fins for the pass-gate (PG) NFET, pull-up (PU) PFET, and pull-down (PD) NFET are generally different. In addition, in SRAM devices, NFET and PFET regions are relatively close to each other, which can result in unwanted merging.
However, it has also been recognized that growing epitaxy to merge source drain regions beneficially reduces access resistance and facilitates formation (e.g., opening and filling) of subsequent conventional contact modules using, for example, contact area (CA) stud lithography.
Accordingly there is a need for a FinFET device and method of forming same that prevents or eliminates the noted difficulties with the epitaxy growth process while maintaining its benefits related to access resistance for the FinFET device.